Fine Grain Synchronisation in VSM Architectures

This paper presents a new scheme to replace course grain barriers with ne grain synchronisation in virtual shared memory systems. Traditionally, shared memory programming models separate data access from synchronisation. In our scheme synchronisation between both writes and their subsequent reads, and reads and their following writes, is achieved through the coherence tags associated with each coherence unit. All potential latency hiding for the data is utilised as, an asynchronous update is sent as soon as new data is available and an asynchronous exclusive message is sent as soon as a copy of data is no longer required. The associated coherence traac is also removed. Performance improvements are presented for two codes 1 , representing the core communication found in shallow (a well known numerical weather prediction benchmark), and CG (from the NAS parallel benchmarks). These are run on a 30 processor EDS prototype, with sequentially consistent invalidation based VSM. Although implemented in software there is much potential to support these optimisations in hardware. Currently these optimisations are performed by the programmer but there is also much scope for automating this process within a compiler.